 
module top(
  input clk_50M,
  input reset,
  output [4:0] led,
 
//  5V
//GND
output uart_txd,
input  uart_rxd,
//sdcard
input   spi_MISO,
output  spi_MOSI,
output  spi_SCLK,
output  spi_CS,

output                   mem_odt,
output                   mem_cs_n,
output                   mem_cke,
output           [13:0]  mem_addr,
output           [2:0]   mem_ba,
output                   mem_ras_n,
output                   mem_cas_n,
output                   mem_we_n,
output           [3:0]   mem_dm,
inout                    mem_clk,
inout                    mem_clk_n,
inout           [31:0]   mem_dq,
inout           [3:0]    mem_dqs,

input        USB3_UART_IN,
output       USB3_RST_OUT,
output       USB3_PCLK,
inout [31:0] USB3_DQ,
output [1:0] USB3_A,
output       USB3_SLCS_N,
output       USB3_SLWR_N,
output       USB3_SLOE_N,
output       USB3_SLRD_N,
output       USB3_PKTEND_N,
input        USB3_FLAGA,
input        USB3_FLAGB,
output        USB3_FLAGC,//USB3_CMD_SIGNAL
input        USB3_FLAGD,//USB3_CMD_CS
input        USB3_CMD_CLK,
input        USB3_CMD_DAT_U2F,
output       USB3_CMD_DAT_F2U,


  input flash_miso,
  output flash_mosi,
  output flash_cs,
  output flash_clk,


  output video_hs,
  output video_vs,
  output [15:0] video,
  
  input dummy
);

wire myuart_rxd = uart_rxd;

assign uart_txd = USB3_UART_IN;

//sdcard
//input   spi_MISO,
//output  spi_MOSI,
//output  spi_SCLK,
//output  spi_CS,

//input        USB3_FLAGD,//USB3_CMD_CS
//input        USB3_CMD_CLK,
//input        USB3_CMD_DAT_U2F,
//output       USB3_CMD_DAT_F2U,

assign spi_SCLK = USB3_CMD_CLK;
assign spi_CS = USB3_FLAGD;//USB3_CMD_CS
assign spi_MOSI = USB3_CMD_DAT_U2F;
assign USB3_CMD_DAT_F2U = spi_MISO;

wire src;
altsource_probe	altsource_probe_component (
			.probe (0),
			.source (src)
			);
defparam
	altsource_probe_component.enable_metastability = "NO",
	altsource_probe_component.instance_id = "MINV",
	altsource_probe_component.probe_width = 32,
	altsource_probe_component.sld_auto_instance_index = "YES",
	altsource_probe_component.sld_instance_index = 1,
	altsource_probe_component.source_initial_value = " 0",
	altsource_probe_component.source_width = 32;

assign USB3_FLAGC = src;

assign USB3_RST_OUT = rst_count[25] ? 1'bz : 1'b0;
reg [25:0] rst_count;
always @(posedge clk_50M or negedge reset) begin
  if (!reset) begin
    rst_count <= 0;
  end else begin
    if(!rst_count[25])begin
      rst_count <= rst_count + 1'b1;
    end
  end
end






reg sys_rst_n ;// && locked_sdram && locked_cpu && locked_vga;
reg [20:0] reset_delay;
always @(posedge clk_50M or negedge reset) begin
  if (!reset) begin
    reset_delay <= 0;
     sys_rst_n <= 0;
  end else begin
    reset_delay <= reset_delay+1'b1;
     if(reset_delay[20])begin
        sys_rst_n <= 1;
     end
  end
end


assign led[0] = flg;
assign led[1] = flg2;
assign led[2] = 1;
assign led[3] = 1;
assign led[4] = video_busy;

reg [31:0] cnt;
reg flg;
always @(posedge clk_50M or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    cnt <= 0;
    flg <= 1;
  end else begin
    cnt <= cnt+1'b1;
     if(cnt==32'd50000000)begin
        cnt <= 0;
        flg <= ~flg;
     end
  end
end

reg [31:0] cnt2;
reg flg2;
always @(posedge mem_clk or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    cnt2 <= 0;
    flg2 <= 1;
  end else begin
    cnt2 <= cnt2+1'b1;
     if(cnt2==32'd50000000)begin
        cnt2 <= 0;
        flg2 <= ~flg2;
     end
  end
end






  wire             ctl_clk;
  wire    [ 13: 0] afi_addr;
  wire    [  2: 0] afi_ba;
  wire             afi_cas_n;
  wire             afi_ras_n;
  wire             afi_cs_n;
  wire             afi_we_n;
  wire             afi_rst_n;

  wire             afi_cke;
  wire             afi_ctl_long_idle;
  wire             afi_ctl_refresh_done;

  wire             afi_odt;
  wire    [  3: 0] afi_rdata_en;
  wire    [  3: 0] afi_rdata_en_full;
  wire             afi_cal_fail;
  wire             afi_cal_success;
  wire             afi_mem_clk_disable;

  wire             ctl_reset_n;




wire local_init_done = afi_cal_success;

localparam CFG_MEM_IF_CS_WIDTH = 1;
localparam CFG_AFI_INTF_PHASE_NUM = 2;
localparam CFG_MEM_IF_BA_WIDTH = 3;
localparam CFG_MEM_IF_ROW_WIDTH = 14;
localparam CFG_MEM_IF_COL_WIDTH = 10;
localparam CFG_INT_SIZE_WIDTH = 4;

wire [CFG_MEM_IF_ROW_WIDTH - 1 : 0]   seq_ac_addr;//14
wire [CFG_MEM_IF_BA_WIDTH - 1 : 0]    seq_ac_ba; //3
wire                                  seq_ac_cas_n;//8
wire                                  seq_ac_ras_n;
wire                                  seq_ac_we_n;
wire                                  seq_ac_cke;
wire                                  seq_ac_cs_n;
wire                                  seq_ac_odt;
wire                                  seq_ac_rst_n;
wire                                  seq_ac_sel;



wire [(CFG_MEM_IF_CS_WIDTH)  - 1 : 0] bg_to_chipsel;
wire [(1                  )  - 1 : 0] bg_to_chip;
wire [(CFG_MEM_IF_BA_WIDTH)  - 1 : 0] bg_to_bank;
wire [(CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
wire [(CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;

wire [CFG_MEM_IF_CS_WIDTH    - 1 : 0] cmd_gen_chipsel;
wire [CFG_MEM_IF_BA_WIDTH    - 1 : 0] cmd_gen_bank;
wire [CFG_MEM_IF_ROW_WIDTH   - 1 : 0] cmd_gen_row;
wire [CFG_MEM_IF_COL_WIDTH   - 1 : 0] cmd_gen_col;
wire do_refresh;
wire my_do_activate;
wire my_do_write;
wire my_do_read;
wire my_do_auto_precharge;
wire my_do_precharge;

assign bg_to_chipsel = cmd_gen_chipsel;
assign bg_to_chip = 1'b1;
assign bg_to_bank = cmd_gen_bank;
assign bg_to_row = cmd_gen_row;
assign bg_to_col = cmd_gen_col;



wire  [  7: 0] afi_dm;
wire  [ 63: 0] afi_wdata;// = sdram_din;
wire [31:0] dio_rdata;
wire [63:0] dio_rdata64;
wire           afi_dqs_burst;
wire           afi_wdata_valid;
wire measure_clk_2x;

wire usb_clk;// usb_clk_out 的话，pc2fpga 少等一个周期，          rd <= 1;          ft_status <= 3;      usb3_cnt==usb3_cnt_max-1
assign USB3_PCLK = usb_clk;
pll_usb pll_usb_inst(
  .areset  (~reset),
  .inclk0             (clk_50M),
  .c0                 (usb_clk),
  .c1                 (usb_clk_out),
  .locked             ()
);


  
//assign K22 = vga_hs ^ vga_vs ^ (video_de ? 0 : (|vga_rgb)) ^ audio_pwm;
assign video_hs = vga_hs;
assign video_vs = vga_vs;
assign video = vga_rgb;

wire vga_hs;
wire vga_vs;
wire [15:0] vga_rgb;
wire video_de;


wire sdram_idle;
wire sdram_rw_req;
wire sdram_rw_ack;
wire sdram_read_or_write;
wire [31:0] sdram_rw_addr;
wire [ 8:0] sdram_rw_burst;
wire [31:0] sdram_din;
wire [31:0] sdram_dout;
wire [3:0]  sdram_mask;


wire sdram_clk = ctl_clk;
wire sdram_clk_2x = measure_clk_2x;


wire cpu_clk;
wire vga_clk_65M;

cpu_pll cpu_pll_inst(
  .areset	(~reset),
  .inclk0             (clk_50M),
  .c0                 (cpu_clk),
  .c1                 (),
  .locked             ()
);
 
pll_vga pll_vga_inst(
  .areset	(~reset),
  .inclk0             (clk_50M),
  .c0                 (vga_clk_65M),
  .c1                 (),
  .locked             ()
);
 

wire [7:0] ch375_d = 0;
wire video_busy;

endmodule
